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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Industrial Time Base Generator
The MC14566B industrial time base generator is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. This device consists of a divide-by-10 ripple counter and a divide-by-5 or divide-by-6 ripple counter to permit stable time generation from a 50 or 60 Hz line. By cascading this device as divide-by-60 counters, seconds and minutes can be counted and are available in BCD format at the circuit outputs. An internal monostable multivibrator is included whose output can be used as a reset or clock pulse providing additional frequency flexibility. Also a pin has been included to allow divide-by-5 counting for generating 1.0 Hz from European 50 Hz line. Pin 11 = VDD will cause / 5. * * * * * * Negative Edge Triggered Counters for Ease of Cascading Pulse Shapers on Counter Inputs Accept Slow Input Rise Times Monostable Multivibrator Positive or Negative Edge Triggered Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
MC14566B
L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
D SUFFIX SOIC CASE 751B
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage Value Unit V V mA mW - 0.5 to + 18.0 10 500 - 65 to + 150 Vin, Vout Iin, Iout PD Tstg Input or Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature - 0.5 to VDD + 0.5
TA = - 55 to 125C for all packages.
PIN ASSIGNMENT
CA RESET Q0A Q1A Q2A Q3A B VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD CB Q2B Q1B
_C
TL Lead Temperature (8-Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
B5/B6
Qm A
Q0B
BLOCK DIAGRAM
Q0A Q1A Q2A Q3A 3 4 5 6
CA / 10
1
PULSE SHAPER
C R
BCD OUT
RESET / 5// 6 CONTROL
2 11 R Q0B Q1B 12 13 14 BCD OUT
CB / 5// 6
15
PULSE SHAPER
C
Q2B
B A
REV 3 1/94
7 9
MONO- STABLE MULTI- VIBRATOR
10
Qm
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14566B 1
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc IT IT = (1.0 A/kHz) f + IDD IT = (2.0 A/kHz) f + IDD IT = (3.0 A/kHz) f + IDD Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14566B 2
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time, Clock to Q3A tPLH, tPHL = (1.7 ns/pF) CL + 1365 ns tPLH, tPHL = (0.66 ns/pF) CL + 497 ns tPLH, tPHL = (0.5 ns/pF) CL + 295 ns Propagation Delay Time, Reset to Q3A tPHL = (1.7 ns/pF) CL + 845 ns tPHL = (0.66 ns/pF) CL + 282 ns tPHL = (0.5 ns/pF) CL + 185 ns Clock Pulse Width Symbol tTLH, tTHL VDD 5.0 10 15 5.0 10 15 5.0 10 15 tWH(cl) 5.0 10 15 Reset Pulse Width tWH(R) 5.0 10 15 Clock Pulse Frequency fcl 5.0 10 15 Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 10 15 5.0 10 15 1200 400 300 -- -- -- 1.0 2.5 4.2 0.3 1.0 1.5 -- No Limit 1200 400 270 400 125 90 -- -- -- MHz 1200 400 270 400 125 90 -- -- -- ns Min -- -- -- -- -- -- -- -- Typ # 100 50 40 Max 200 100 80 Unit ns tPLH, tPHL ns 1450 530 320 930 315 210 4500 1500 1000 ns 3000 1000 750 ns tPHL Monostable Multivibrator Pulse Width tWH(Qm) 2800 900 600 -- -- -- ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD 500 F Vin Vin PULSE GENERATOR CA CB RESET / 5// 6 CONTROL B A Q0A Q1A Q2A Q3A Q0B Q1B Q2B Qm VSS CL CL CL CL CL CL CL CL 20 ns 90% 50% 10% VARIABLE WIDTH 20 ns VDD VSS ID
Figure 1. Power Dissipation Test Circuit and Waveform
MOTOROLA CMOS LOGIC DATA
MC14566B 3
VDD
PROGRAMMABLE PULSE GENERATOR
CA CB RESET / 5// 6 CONTROL B A
Q0A Q1A Q2A Q3A Q0B Q1B Q2B Qm VSS CL CL CL CL CL CL CL CL
NOTE: Assume / 10 Counter at "6" and / 5/ / 6 Counter at "2" at beginning of sequence. 20 ns / 10 OR / 5// 6 90% CLOCK AND B 10% fcl 10% tPLH 90% 10% tPLH 50% Qm tWH(Qm) tTLH tTHL 50% t WHQm 50% tWH(cl) 50% 20 ns 90% RESET 50% tWH(R) tPHL
Q3A OR Q2B
Figure 2. Switching Time Test Circuit and Waveforms
MC14566B 4
MOTOROLA CMOS LOGIC DATA
TIMING DIAGRAM Divide-By-10 Counter
0 CLOCK 1 2 3 4 5 6 7 8 9 0 1
RESET
Q0
Q1
Q2
Q3
Divide-By-5/Divide-By-6
0 CLOCK 1 2 3 4 5 0 1 2 3 4 0
RESET
CONTROL / 5// 6 Q0
Q1
Q2
Monostable Multivibrator
A
B
Qm = DON'T CARE
MOTOROLA CMOS LOGIC DATA
MC14566B 5
APPLICATION -- 12 HOUR CLOCK
/ 5// 6 < 1.0 M* 60 Hz > 1500 pF* C Q0 Q1 Q2 C
/ 10 Q0 Q1 Q2 Q3 TENTH SECONDS A B Qm
VDD
/ 10 C Q0 Q1 Q2 Q3 SECONDS C
/ 5// 6 Q0 Q1 Q2 A B Qm
+ VDD
/ 10 C Q0 Q1 Q2 Q3 MINUTES C
/ 5// 6 Q0 Q1 Q2 A B Qm
A B C MC14011B / 10 Q0 C Q1 Q2 R Q3 C HOURS / 5// 6 Q0 Q1 R Q2 A B Qm
D
/ 5/ / 6 Control not shown = VSS Reset pins not shown = VSS * Care must be taken in the indicated circuit to filter line transients which may cause "false" counting.
MC14566B 6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MOTOROLA CMOS LOGIC DATA
MC14566B 7
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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MC14566B 8
*MC14566B/D*
MOTOROLA CMOS LOGIC DATA MC14566B/D

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